The variations in process parameters increase with technology scaling. Process variation includes global systematic variation and local device mismatch, as shown at 102, 104, respectively in FIG. 1. Both components increase with scaling and limit circuit yield. The effects of variation are particularly significant for design of static random access memory (SRAM). Thus, characterization of local mismatch and global systematic variation is quite pertinent for SRAM yield.
Local random variation in transistors increases with technology scaling and can degrade circuit robustness. Due to random variations, such as random dopant fluctuation (RDF) or line-edge roughness (LER), neighboring transistors in a die can have significant mismatch in their characteristics. The effect of this local randomness is most pronounced in area-constrained circuits, such as SRAM cells, and limits the density scaling. Hence, measurement, characterization, and modeling of local random variability in the process are of interest for yield learning and yield enhancement in nano-scaled technologies, particularly, for SRAM design. Traditionally, mismatch characterization between neighboring devices is performed by measuring the current difference between nominally identical transistors, such as 202 and 204 in FIG. 2, and extracting the threshold voltage (Vt) difference from the current difference using complex data extraction tools. This method requires sophisticated analog measurements and complex data extraction methods, which significantly increase the test-time, and make it unsuitable for in-line and/or on-chip characterization.
The systematic variations in cell transistors also significantly impact cell failures. As shown in FIG. 3, traditionally, the systematic variation is characterized by distributing on-chip ring-oscillators 302 across a chip and measuring the frequency. However, such a measurement cannot accurately predict the systematic variation in SRAM cell (systematic variation is a strong function of cell layout).
The conventional 6-transistor (6T) SRAM 400, depicted in FIG. 4, includes a first inverter formed by p-type and n-type field effect transistors (PFET and NFET, respectively) PL and NL (numbered 402 and 404), cross-coupled to a second inverter formed by PFET PR and NFET NR, numbered 406, 408. The cross-coupled inverters are connected to a voltage supply node 410 and a ground 412. Left and right NFET access devices SL, SR, numbered 414 and 416, interconnect true bit line 418 and complementary bit line 420 to storage nodes 426, 424 under control of word line 422.